1. Field of the Invention
The present invention relates to a differential amplifier circuit and a semiconductor device including the same, and more particularly to a differential amplifier circuit that is suitably used to an internal voltage generation circuit, and a semiconductor device including the same.
2. Description of Related Art
In many semiconductor devices, an internal voltage generation circuit that generates an internal voltage based on an external voltage is provided. What is known as the internal voltage generation circuit is of a type that uses a differential amplifier circuit, as disclosed in Japanese Patent Application Laid-Open No. 2005-208692 and K. Itoh, M. Horiguchi, H. Tanaka, Ultra-Low Voltage Nano-Scale memories, New York: Springer, 2008, (pp amp.: pp. 238-239, p-z comp.: pp. 253-261).
FIG. 12 is a circuit diagram of a conventional differential amplifier circuit disclosed in K. Itoh, M. Horiguchi, H. Tanaka, Ultra-Low Voltage Nano-Scale memories.
A differential amplifier circuit shown in FIG. 12 includes transistors M4 and M5 connected into a differential form and a transistor M6 connected in common to the transistors M4 and M5. The gate electrode of the transistor M4 is supplied with a reference voltage VREF. The gate electrode of the transistor M5 is supplied with an output voltage Vout. The gate of the transistor M6 is supplied with a bias voltage VB1.
A current flowing through the transistor M4 is supplied into a current mirror circuit CM2 that includes transistors M1 and M7. An output current thereof is supplied into a current mirror circuit CM3 that includes transistors M9 and M10. Meanwhile, a current flowing through the transistor M5 is supplied into a current mirror circuit CM1 that includes transistors M3 and M8. As shown in FIG. 12, the transistors M8 and M10 that constitute output transistors of the current mirror circuits CM1 and CM3 are connected in series. As a result, a difference current between an output current flowing through the transistor M8 and an output current flowing through the transistor M10 flows through an output node N1 . The output node N1 is connected to the gate electrode of a driver transistor M11. Accordingly, the conduction state of the driver transistor M11 is so controlled that the level of the output voltage Vout becomes equal to the reference voltage VREF.
However, according to a study by the present inventor, the response speed of the differential amplifier circuit shown in FIG. 12 is not enough. Moreover, the voltage gain is relatively low. Therefore, there is obviously the problem that an output voltage error is large. In order to increase the response speed, the current ratio of the current mirror circuits CM1 and CM2 should be so designed as to be 1: k, where k<1. However, in this case, the output current of the current mirror circuits CM1 and CM2 becomes 1/k times larger, resulting in an increase in power consumption. Even if the current ratio of the current mirror circuits CM1 and CM2 is 1:k, the voltage gain remains unchanged, meaning that the output voltage error is not reduced. Therefore, what is desired is a differential amplifier circuit that has a fast response speed and a smaller output voltage error.